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Features
* PWM and Direction-controlled Driving of Four Externally Powered NMOS Transistors * Internal Charge Pump Provides Gate Voltages for High-side Drivers in Permanent ON
Mode and Supplies the Gate of the External Battery Reverse Protection NMOS
* 5V Regulator With External Power Device (NPN) and Current Limitation Function * Reset Derived From 5V Regulator Output Voltage * Sleep Mode With Supply Current of Typical 35 A, Wake-up by Signal on Pin EN or on * * * * * *
SCI Interface (Pin /DATA) Window Watchdog; the Watchdog Time is Programmable by Choosing a Certain Value of the External Watchdog Capacitor CCWD and the External Watchdog Resistor RCWD Battery Overvoltage Protection and Battery Undervoltage Management Overtemperature Protection SCI Transceiver (Operating in Differential or Single-ended Mode) for Use at Battery Voltage Level Digital Control Block With the Control Pins EN, DIR, PWM Internal Low-power Regulator With Low-power Band Gap (Trimmed With Four Bits) to Guarantee Power Dissipation in Sleep Mode and to Guarantee Parameters for Wake-up
H-bridge Motor Driver ATA6026
1. Description
The ATA6026 is used to drive a continuous-current motor in a full H-bridge configuration. An external microcontroller controls the driving function of the ATA6026 by providing a PWM signal and a direction signal, and allows the usage of the ATA6026 in a windshield wiper application, for example. The ATA6026 supports PWM and direction-controlled driving of four external power MOSFETs with two external bootstrap capacitors. The PWM control is performed by the high-side switch. The opposite low-side switch is permanently ON in the driving phase. Motor braking is performed using the low-side switches. A programmable dead time is included to prevent peak currents within the H-bridge. The maximum PWM frequency is 30 kHz.
Rev. 4865C-AUTO-01/06
Figure 1-1.
Block Diagram
M
RGATE VBATSW H1
RGATE H2 CB1 S1 S2
RGATE CB2 L1
RGATE L2
HS Driver 1
HS Driver 2
Bootstrap 1
Bootstrap 2
LS Driver 1
LS Driver 2
DG2 DG1
DG2 DG1
VINT Vint 5V Regulator
Charge Pump
13V Regulator
Band Gap
Oscillator
VBAT
OTP DC
VCC
CC VRefCC
VCC 5V Regulator VSHUNT VREG VBAT Bias VREF
Logic Control
UV OV
Supervisor
OT
PGND GND
VBAT VBAT Vint Watchdog CP CP VBAT DATA Reset SCI
/DATA
EN VCC
/RESET
WD CWD
DIR
PWM
RX
TX
SEM
RSEM
Battery
Microcontroller
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2. Pin Configuration
Figure 2-1. Pinning QFN32
VINT GND VREF VBAT_SWITCH SEM EN PWM DIR VREG VSHUNT VCC DATA /DATA VBAT CP PGND 1 2345678 32 9 10 31 30 Atmel YWW 11 29 12 ATA6026 13 28 ZZZZZ-AL 14 27 15 26 16 25 24 23 22 21 20 19 18 17 L1 L2 H1 S1 CB1 CB2 S2 H2 DG1 DG2 /RESET RX TX WD CWD CC
Note:
YWW ATA6026 ZZZZZ AL
Date code (Y = Year above 2000, WW = week number) Product name Wafer lot number Assembly sub-lot number
Table 2-1.
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Pin Description
Symbol VINT GND VREF VBAT_SWITCH SEM EN PWM DIR DG1 DG2 /RESET RX TX WD CWD Function Supply Pin Analog in Analog out (HV) Digital input-PU Digital input (HV) PD Digital input (HV) PD Digital input (HV) PD Digital output Digital output Open drain-PU Digital output-PU Digital input-PU Digital input Analog in/out Description Output of internal voltage regulator (external blocking capacitor) Ground, substrate of ATA6026 Reference resistor for reference current Connected with VBAT via an ATA6026-internal switch Control of SCI mode (Single-ended Mode) Enable control input PWM control input Direction control input Status output 1 Status output 2 Reset output, active low Data output pin of SCI interface Transmit control input for SCI interface Watchdog trigger input Capacitor for definition of watchdog timer ESD Protection Open drain 14V + diode to GND + diode from VCC Diode to PGND Open drain 14V + diode to GND Diodes to VBAT/GND Diodes to GND/VCC Open drain HV + diode to GND Open drain HV + diode to GND Open drain HV + diode to GND Diodes to GND/VCC Diodes to GND/VCC Diodes to GND/VCC Diodes to GND/VCC Diodes to GND/VCC Diodes to GND/VCC Diodes to GND/VCC
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Table 2-1.
Pin 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Pin Description (Continued)
Symbol CC H2 S2 CB2 CB1 S1 H1 L2 L1 PGND CP VBAT /DATA DATA VCC VSHUNT VREG Function Analog in Analog out (HV) Analog in/out (HV) Analog in/out (HV) Analog in/out (HV) Analog in/out (HV) Analog out (HV) Analog out (HV) Analog out (HV) Pin Analog out (HV) Supply (HV) Analog in/out (HV) Analog in/out (HV) Supply Analog in Analog out Description Cross conduction time definition Gate of external high-side NMOS 2 Source of external high-side NMOS 2 Boost capacitor 2 voltage input Boost capacitor 1 voltage input Source of external high-side NMOS 1 Gate of external high-side NMOS 1 Gate of external low-side NMOS 2 Gate of external low-side NMOS 1 Power ground (used for drivers and power devices of charge pump) Charge pump output Battery voltage behind the reverse protection element Inverse data signal of SCI Data signal SCI (high voltage + modulation) Feedback of regulated VCC and main supply of low voltage part of ATA6026 Sense input for current limitation in VCC regulator Base of external regulator pass device (NPN) ESD Protection Diodes to GND/VCC Floating open drain HV + diode to CB2 Floating open drain HV + diode to H2 Open drain HV + diode to GND Open drain HV + diode to GND Floating open drain HV + diode to H2 Floating open drain HV + diode to CB1 Open drain HV + diode to GND Open drain HV + diode to GND Diode to GND Open drain HV + diode from VBAT + diode to GND Open drain HV + diode to CP + diode to GND Floating open drain HV Floating open drain HV Open drain 14V + diode to GND Diodes to GND and VCC Open drain 14V + diode to GND
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3. Functional Description
3.1
3.1.1
Power Supply Unit
Power Supply The ATA6026 is supplied by a reverse-protected battery voltage. To prevent damage to the IC, proper external protection circuitry must to be added. Use of a capacitor combination of storage and HF capacitors behind the reverse protection circuitry and closed to the VBAT pin of the ATA6026 (Figure 1-1 on page 2) is recommended. A fully-internal low-power and low-drop regulator with a voltage of 5V and cleaned by an external blocking capacitor provides the necessary low-voltage supply needed for the wake-up process. The low-power band gap is trimmed by OTPDC and is also used for the big regulator. The following blocks are supplied by the internal regulator: * Enable input comparator * Band gap * Wake-up part of the SCI interface * Digital control of the complete ATA6026 * OTPDC * VCC regulator (5V external) The internal supply voltage VINT must not be used for any other supply reasons! All the remaining blocks are supplied by the VCC regulator (5V). For detection reasons by microcontroller, there is a high-voltage switch which brings out the battery voltage to the pin VBAT_SWITCH. This switch is ON for VCC > VthRES.
3.2
Sleep Mode
Sleep mode exists to guarantee the low quiescent current of the inactive ATA6026. In Sleep mode it is possible to wake up the IC by using the pins EN or /DATA. The following blocks are active in Sleep mode: * Band gap * Internal 5V regulator with external blocking capacitor of 100 nF * Input structure for detecting the EN pin threshold * Wake-up block of SCI receive part
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3.3
Wake-up and Sleep Mode Strategy
The ATA6026 has 2 modes: Sleep and Active. To change between the two modes, 3 procedures are implemented and described here. The default state after power-on is Active mode. 1. Go to Sleep A HIGH to LOW transition at pin EN, followed by a LOW for the time tgotosleep (typically 50 ms), switches the ATA6026 to Sleep mode. The internal 5V supply VINT, the EN pin input structure, and a certain part of the SCI receiver are permanently active to ensure proper startup of the system. 2. Go to Active by activating pin EN The input structure on pin EN consists of a comparator with built-in hysteresis. The input of the comparator is protected against voltages up to VBATmax. Pulling the EN pin up to HIGH for a time longer than twakeEN (typically 50 ms) will switch the ATA6026 to Active mode. 3. Go to Active via the SCI interface The second possibility for waking up the part is to use the SCI transceiver. In Sleep mode the SCI receiver is partially active and works in single-ended mode, independent of the status of the pin SEM. The wake-up by SCI requires 2 steps: a. If the voltage on pin /DATA is below a value of V/DATwake (about VVBAT - 2V), the receive part of the SCI interface is active (not to be confused with Active mode of the whole IC). The active receive part is able to detect a valid LOW on the /DATA pin. b. If /DATA is LOW for a filter time twakeSCI (typically 50 ms), the IC will change to Active mode. A short change back to HIGH during the filter time will reset the filter. After entering the Active mode, this information is stored in a latch.
When the SCI interface is used to switch to Active mode, the EN pin can remain LOW without disturbing the Active mode status. Figure 3-1 on page 7 illustrates the wake-up by SCI.
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Figure 3-1. Wake-up by SCI, Pin /DATA
/DATA VBAT 45% 55% Level activating PREWAKE 2
EN
REC_SCI
twakeSCI
t < twakeSCI STATUS Active
twakeSCI
tdelON_EN
tgotosleep
Sleep
The status PREWAKE is characterized by the activated receive block of SCI and activated comparator of EN input. After going to Active, the VCC regulator starts working. "Go to Sleep" is possible via a valid HIGH to LOW transition at pin EN (remaining LOW for longer than tgotosleep), if EN was previously in a valid HIGH state (HIGH for longer than tdelON_EN).
3.4
5V Regulator
The 5V regulator is on-chip, using an external NPN as the power element. The reason behind using an external pass device is to prevent large power dissipation within the ATA6026. For a battery voltage level between 6V and 9V, the regulated output voltage is 5V 10%; above VVBAT 9V, the regulated output voltage is 5V 3%. To prevent the destruction of the external NPN and the ATA6026, a sense resistor is used to detect the current delivered by the regulator. In case of overcurrent, the regulator limits the current to the specified level. This means that if the characteristic of the voltage regulator changes to the characteristic of a current regulator, the delivered voltage will break down. To function correctly, the regulator requires an external NPN transistor with a minimum BN of 25.
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Figure 3-2.
Principal Function of the 5V Regulator with External Pass Device
Battery
VBAT VREG VSHUNT RSENSE VCC RESR CELKO CHF
3.5
Reset and Watchdog Management
The reset and watchdog management block controls the pin /RESET and influences the behavior of the internal circuitry. The /RESET pin is active low with an internal pull-up resistor to VCC. * Static reset dependent on VCC level The reset will be active for VCC < VtHRESx. The level VtHRESx is realized with a hysteresis (HYSRESth).
Figure 3-3.
Static Reset Behavior
VCC VtHRESH VtHRESL
t
/RESET
tdelayRESH
tdelayRESL
tdelayRESH
t
* Dynamic reset dependent on watchdog behavior
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Figure 3-4 shows the principal behavior of the watchdog. An RC oscillator composed of the external elements RCWD and CCWD defines the timing base of the watchdog (referred to here as t). t(s) = tdis(s) + 1.1 x RCWD(k) x [CCWD(nF) + Cparasitic(nF)] tdis = 1.83 s (Cparasitic is assumed to be 10 pF (pad capacitance + wiring capacitance on PCB)) The watchdog is realized as a window watchdog and will be triggered by the microcontroller via a LOW to HIGH transition at pin WD during the open window. If the watchdog detects a window error (no trigger in open window or wrong trigger in closed window), a reset pulse of length tres will be generated. To relieve the watchdog trigger after power-on, the first open window is longer by a factor of about 4.5 compared to the following windows. tOW = t x 185 (open window) tCW = t x 185 (closed window) tOW1 = t x 832 (first open window after power-on) tres = t x 43 (reset pulse length) Figure 3-4. Principal Behavior of the Watchdog
tres /RESET tow1 tcw tow tcw tow tow1 tres
WD
Figure 3-5.
External Elements of the Watchdog
VCC
RCWD CWD CCWD
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Table 3-1.
Examples of Watchdog Oscillator Period t (s) as a Function of CCWD and RCWD
CCWD (pF) RCWD (k) 100 81 75 68 62 56 51 47 43 39 36 33 30 27 24 22 20 18 16 15 13 12 10 3300 366.0 296.9 275.1 249.6 227.8 206.0 187.8 173.3 158.7 144.2 133.3 122.4 111.4 100.5 89.6 82.4 75.1 67.8 60.5 56.9 49.6 46.0 38.7 2200 245.1 199.0 184.4 167.4 152.9 138.3 126.2 116.5 106.8 97.0 89.8 82.5 75.2 67.9 60.6 55.8 50.9 46.1 41.2 38.8 33.9 31.5 26.6 1000 113.3 92.2 85.6 77.8 71.1 64.5 58.9 54.5 50.1 45.6 42.3 39.0 35.6 32.3 29.0 26.8 24.5 22.3 20.1 19.0 16.8 15.7 13.4 810 92.4 75.3 69.9 63.6 58.2 52.8 48.3 44.7 41.1 37.5 34.8 32.1 29.4 26.7 24.0 22.2 20.4 18.6 16.8 15.9 14.1 13.2 11.4 680 78.2 63.8 59.2 53.9 49.3 44.8 41.0 38.0 34.9 31.9 29.6 27.4 25.1 22.8 20.5 19.0 17.5 16.0 14.5 13.7 12.2 11.4 9.9 560 65.0 53.1 49.3 44.9 41.2 37.4 34.3 31.8 29.3 26.8 24.9 23.0 21.1 19.3 17.4 16.1 14.9 13.6 12.4 11.7 10.5 9.9 8.6 100 14.4 12.1 11.4 10.6 9.8 9.1 8.5 8.0 7.5 7.1 6.7 6.3 6.0 5.6 5.3 5.0 4.8 4.5 4.3 4.2 3.9 3.8 3.6
Do not use capacitors greater than 3.3 nF or less than 470 pF Do not use resistors less than 10 k or greater than 100 k Do not apply periods shorter than 11.5 s (f < 85 kHz is to be used) For a typical application with C = 1 nF and R = 56 k, we will get the following values: tres = 2.77 ms tow = tcw = 11.9 ms tow1 = 53.66 ms The internal tolerance is < 6.5%; tolerances of external elements have to be included into the period calculation.
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3.6 SCI Transceiver
The SCI transceiver is a differential device which can also work in single-ended mode. In singleended mode the levels and the currents are compatible with the LIN interface, but use a faster timing. It is necessary to define the SCI differential mode by externally pulling down the pin SEM. Single-ended mode is the default if the pin SEM is left open. In this case, the /DATA pin is active. The typical external elements on pin DATA are also recommended for single-ended mode (SEM mode). The driver on pin DATA is passive in single-ended mode. SEM is a digital input pin with an internal pull-up resistor to VCC. So, in Sleep mode no current will flow through the pull-up resistor and affect the Sleep mode supply current, as the VCC regulator is down while in Sleep mode. Figure 3-6. Principal Function of SCI
ACTIVE
1
VCC SCIREC RS
VBAT
1 k 1 nF /DATA
wake_SCI SCI_Rx
SW3
SW2 LINM 1 nF RS SW1 ACTIVE 10 k 1 k DATA
& 1
SCI_Tx
Switches SW1, SW2, SW3 are ON for control signals = HIGH
RS: both resistors provide VVBAT/2
Definition of symbols in Figure 3-6: ACTIVE: SCIREC: VCC: wake_SCI: SCI_Rx: SEM: VVBAT: ATA6026 is in Active mode Receive part of SCI is working VCC voltage (pin VCC) Wake-up by SCI performed (for more information on the filter time twakeSCI, see"Wake-up and Sleep Mode Strategy" on page 6) Rx output of SCI Single-ended mode of SCI when SEM = HIGH (SEM = "Single-ended Mode") Voltage at pin VBAT (not car battery!)
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Figure 3-7.
Timing of SCI (Differential Mode)
Tx
0.7 x VCC 0.3 x VCC tSCf tSCL Vhdiff 80% 0.05 x VBAT 0 -0.05 x VBAT Vldiff Rx 20% t tRxL tRxH 0.7 x VCC 0.3 x VCC t tSCH tSCr t
/DATA - DATA
Vhdiff = VVBAT (SCI driver is passive, recessive mode) Vldiff = VT/DATAL - VTDATAH (VT/DATAL is the output low voltage of pin /DATA) Figure 3-8. Timing of SCI (Single-ended Mode)
Tx
0.7 x VCC 0.3 x VCC tSCf tSCL Vhdiff 80% 0.05 x VBAT 0 -0.05 x VBAT Vldiff Rx 20% t tRxL tRxH 0.7 x VCC 0.3 x VCC t tSCH tSCr t
/DATA - DATA
VT/DATAL is the output low voltage of pin /DATA 12
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When SEM is HIGH (single-ended mode), the reference for the receive comparator will be switched from signal DATA to VVBAT / 2. It is not necessary to do this external of the ATA6026; the signal SEM = HIGH signals this request to the ATA6026. It is recommended, but not necessary, to use the external connections of DATA and /DATA for both differential mode and single-ended mode as specified in Figure 3-6 on page 11. The pin DATA may also be kept open if single-ended mode is programmed.
3.7
Control Inputs EN, DIR, PWM
Pin EN: The enable pin is used to activate the ATA6026 with a HIGH. This input uses low voltage levels but has to withstand a voltage up to 40V. An internal pull-down resistor is included. Pin DIR: Logical input to control the direction of the external motor. An internal pull-down resistor is included. The test mode is entered when this pin is pulled to a voltage above 10V. Pin PWM: Logical input for PWM information delivered by external microcontroller. Duty cycle and frequency of switching can be choosen by this pin. An internal pull-down resistor is included. The test mode is entered when this pin is pulled to a voltage above 10V.
Table 3-2.
Status of the ATA6026 Depending on Control Inputs and Detected Failures (x Means Don't Care)
Device Status TS x 1 0 0 0 0 0 0 0 0 OV x 0 1 0 0 0 0 0 0 0 UV x 0 0 1 0 0 0 0 0 0 SC x 0 0 0 1 0 0 0 0 0 x x x x x PWM PWM 0 1 1 Driver Stage for External Power MOS H1 Off Off Off Off Off PWM Off Off Off On L1 Off Off Off Off Off /PWM On On On Off H2 Off Off Off Off Off Off PWM Off On Off L2 Off Off Off Off Off On /PWM On Off On Diagnostic Outputs DG1 0 1 0 1 1 0 0 0 0 0 DG2 0 1 1 0 1 0 0 0 0 0 Standby mode Thermal shutdown(1) Overvoltage(1) Undervoltage(1) Short circuit(1) Motor PWM forward Motor PWM backward Motor brake Motor full forward Motor full backward Comments
Control Inputs EN 0 1 1 1 1 1 1 1 1 1 Note: DIR x x x x x 0 1 x 1 0 PWM
1. See section "Diagnosis" on page 14 for explanation
TS: Thermal shutdown OV: Overvoltage of VBAT UV: Undervoltage of VBAT SC: Short circuit
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3.8
Diagnosis
Table 3-3.
Event UV
Table of Events Detected by the ATA6026
Description Undervoltage (VBAT < VTHUV) VBAT increasing above VTHUV Overvoltage (VBAT > VTHOV) VBAT increasing above VTHOV Short circuit (if source-drain voltage of switched external NMOS is > 4V, short circuit is detected) Short circuit condition disappears Thermal shutdown (junction temperature > 165oC hysteresis) Thermal shutdown (junction temperature < 165oC hysteresis) DG1 DG2 Additional reaction of ATA6026 1 0 Switch OFF L1, L2, H1, H2 Switch ON L1, L2, H1, H2 according to PWM/DIR status Switch OFF L1, L2, H1, H2 Switch ON L1, L2, H1, H2 according to PWM/DIR status Timing 16 s to 35 s after detection After LOW to HIGH transition at PWM 16 s to 35 s after detection After LOW to HIGH transition at PWM
Release UV
0
0
OV
0
1
Release OV
0
0
SC
1
1
Switch OFF L1, L2, H1, H2
5 s to 15 s after detection
Release SC
0
0
Switch ON L1, L2, H1, H2 according to PWM/DIR status
After LOW to HIGH transition at PWM
TS
1
1
Switch OFF L1, L2, H1, H2, DATA, Directly after /DATA detection Switch ON L1, L2, H1, H2, according to PWM/DIR status After LOW to HIGH transition at PWM
Release TS
0
0
Switch ON DATA, /DATA according Directly after to Tx status detection
Note:
After power-on, the undervoltage status may be latched. To switch the drivers ON, a LOW to HIGH transition at PWM is required.
3.8.1
Overvoltage This block protects the IC and the external power MOS transistors against overvoltage on the battery. Function: In the case of overvoltage alarm (V THOV), the external NMOS transistors will be switched off, and the event will be signalled by switching the pin DG2 ON (see Table 3-3). If the overvoltage condition disappears, after the next LOW to HIGH transition at pin PWM, the drivers for the external power MOS transistors will switch back to the status defined by the control pin DIR and the pin DG2 will be cleared to LOW if there is no other event to be signalled. The SCI drivers are not influenced by the voltage supervisor. The comparator includes a hysteresis.
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3.8.2 Undervoltage This block switches off the external power MOS transistors in case of undervoltage on the battery. Function: In case of undervoltage alarm (VTHuV), the external NMOS transistors will be switched off and the event will be signalled by switching ON the pin DG1 (see Table 3-3 on page 14). If the undervoltage condition disappears, after the next LOW to HIGH transition at pin PWM the drivers for the external power MOS transistors will switch back to the status defined by the control pin DIR, and the pin DG1 will be cleared to LOW if there is no other event be signalled. The SCI drivers are not influenced by the voltage supervisor. The comparator includes a hysteresis. 3.8.3 Temperature Supervisor There is a temperature sensor integrated on-chip to prevent overheating of the ATA6026 and to protect external NMOSFETS from a failure in external circuitry. In case of detected overtemperature (150C to 180C), all drivers including SCI drivers will be switched OFF immediately and both of the diagnostic pins DG1 and DG2 will be switched to HIGH to signal this event to the processor. The status thermal shutdown (TS) will be stored in a latch: After the next LOW to HIGH transition at pin PWM, the drivers for the external power MOS transistors will switch back to the status defined by the control pin DIR, the pins DG1 and DG2 will be cleared to LOW if there is no other event to be signalled, and the SCI drivers immediately will switch to the status defined by the control pin TX. A hysteresis is built in to prevent fast oscillations. Attention: With DG1 = DG2 = HIGH, short circuit is signalled as well as overtemperature. 3.8.4 Short Circuit Detection To detect a short in H-bridge circuitry, internal comparators detect the voltage difference between source and drain of the external power NMOS. If transistors are switched ON and the source drain voltage difference is higher than the value VSC (4V with tolerances) for a time greater than tSC, the signal SC (short circuit) will be set, the external power MOS transistors will be switched off immediately, and the pins DG1 and DG2 will be switched to HIGH to signal this event to the processor. With the next programmed LOW to HIGH transition on pin PWM, the bits will be cleared and the corresponding drivers will switch back to the status defined by the control pin DIR; the pins DG1 and DG2 will switch back to LOW if the short circuit condition has cleared.
3.9
Behavior of the Bridge Drivers in Case of RESET
In case of RESET (/RESET = LOW), the high-side drivers will be switched OFF and the low-side drivers will remain in the status defined by PWM and DIR. In case of overvoltage (OV), undervoltage (UV), thermal shutdown (TS), or short circuit (SC), all the drivers will be switched off, independent of the status of the /RESET pin.
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3.10
Charge Pump
The fully-integrated charge pump is needed to supply the gates of the external power MOSFETs of the HS drivers in case of permanent ON (100% PWM, no bootstrap function is available). In addition, the gate of the external power NMOS used for reverse battery protection is supplied by the charge pump output. The charge pump is fully integrated, including the oscillator with a typical frequency of 2.2 MHz, and works by pumping the regulated 5V three times above the battery. In addition, the charge pump output is supplied by the action of the bootstrap capacitors. If EN is switched to "0" (Sleep mode), the charge pump function is disabled, and the charge pump output voltage will be set to one diode threshold below VBAT.
3.11
H-bridge Driver
The IC includes two push-pull drivers to control two external power NMOS used as high-side drivers, and two push-pull drivers to control two external power NMOS used as low-side drivers. The drivers can be used with either standard or logic-level power NMOS. The drivers for the high-side control use external bootstrap capacitors to supply the gates with a voltage of 8V to 14V above the battery voltage level. The bootstrap capacitor has to be greater than or equal to 10 x C GATE, where CGATE is the capacitance of the external switching NMOS. Smaller values of bootstrap capacitor will reduce the dynamic gate voltage of the external switching NMOS. It is also possible to control the external load (motor) in the reverse direction (see Table 3-3 on page 14). A duty cycle of 100% in both directions is possible, using the charge pump to supply the gates of the high-side drivers. The output voltage of the drivers for the low-side control is limited to a level of less than 16V, but is not clamped active.
3.11.1
Cross Conduction Time To prevent high peak currents in the H-bridge, a non-overlapping phase for switching the external power NMOS is realized. An external RC combination defines the cross conduction time in the following way: tCC (s) = 0.36 x RCC (k) x CCC (nF) + 0.2 (tolerance: 5% 0.15 s) The RC combination is charged to 5V and the switching level of the internal comparator is 67% of the start level. The time measurement is triggered by the PWM or DIR signal crossing the 50% level.
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Figure 3-9. Timing of the Drivers
PWM or DIR
50%
t
tLxHL tLxf tLxLH tLxr
80%
Lx
20%
tCC
t
tHxLH tHxr tHxHL tHxf
tCC
80%
Hx
20%
t
The delays tHxLH and tLxLH include the cross conduction time tCC.
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4. Absolute Maximum Ratings
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Pin Description Ground Power ground Reverse-protected battery voltage VBAT behind internal switch Digital output Digital output Analog input (LV) 5V output, external blocking capacitor Base of external NPN for 5V regulator Cross conduction time capacitor/resistor combination Digital input coming from microcontroller Watchdog timing resistor Digital input direction control Digital input PWM control and test mode Digital input for enable control Digital input SCI mode control 5V regulator output Sense of 5V regulator current Digital output Digital input SCI data pin SCI data pin Bootstrap capacitor pin Source external high-side NMOS Gates external low-side NMOS Gates of external high-side NMOS Charge pump Power dissipation Storage temperature Soldering temperature (10s) Notes: 1. For VVBAT 13.5V 2. May be additionally limited by external thermal resistance Pin Name GND PGND VBAT VBAT_SWITCH /RESET DG1, DG2 VREF VINT VREG CC WD CWD DIR PWM EN SEM VCC VSHUNT RX TX DATA /DATA CBI, CB2 S1, S2 L1, L2 H1, H2 CP Ptot STORE SOLDERING -40 Min 0 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -27 -27
(1) (1)
Max 0 +0.3 +40 VVBAT + 0.3 VVCC + 0.3 VVCC + 0.3 VVCC + 0.3 +7 +7 VVCC + 0.3 VVCC + 0.3 VVCC + 0.3 +25 +25 +40 VVCC + 0.3 +7 +7 VVCC + 0.3 VVCC + 0.3 VVBAT + 2 VVBAT + 2 +45 VVBAT + 2 +25 +45 +50 0.5(2) +150 260
Unit V V V V V V V V V V V V V V V V V V V V V V V V V V V W C C
-0.3 -2 VPGND - 0.3 -2 -0.3
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ATA6026
5. Operating Range
The operating conditions define the limits for functional operation and parametric characteristics of the device. Functionality outside these limits is not implied unless otherwise stated explicitly. Parameters Operating supply voltage Operating supply voltage Operating supply voltage Operating supply voltage Operating supply voltage Operating supply voltage Note:
(1) (2) (3) (4) (5) (6)
Symbol VVBAT1 VVBAT1_a VVBAT2 VVBAT3 VVBAT4 VVBAT5 ambient
Min 7 18 6 3 0 > 25 -40
Max 18 25 <7 <6 <3 40 +125
Unit V V V V V V C
Ambient temperature range under bias 1. Full functionality 2. t 2 min (jump start)
3. H-bridge drivers may be switched off (undervoltage detection) 4. H-bridge drivers are switched off, 5V regulator and charge pump with reduced parameters, RESET works correctly 5. H-bridge drivers are switched off, 5V regulator and charge pump not working, RESET not correct 6. H-bridge drivers are switched off, load dump
6. Temperature Conditions
Junction Temperature/C -40 to +150 150 to 180 Status of IC Normal functionality Drivers for H1, H2, L1, L2, DATA, /DATA may be switched OFF, (DG1 and DG2 will be HIGH in this case), parameters may depart from specified values Drivers for H1, H2, L1, L2, DATA, /DATA are switched OFF and DG1 and DG2 will be HIGH (to signal overtemperature), parameters may depart from specified values. 180C is the maximum switch-off temperature
> 180
19
4865C-AUTO-01/06
7. Electrical Characteristics
All parameters given are valid for 7V VBAT 40V and for -40C ambient 125C unless stated otherwise. Conditions: SEM = HIGH (single-ended mode of SCI). No. 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 1.10 1.11 1.12 Parameters Test Conditions Pin Symbol Min Typ Max Unit Type* Power Supply and Supervisor Functions (This Block Supplies Parts of the ATA6026 Used for Startup and Supervises the VBAT Voltage (Battery Voltage Behind the Reverse Battery Protection Device)) Current consumption VBAT Current consumption VBAT, in standby mode Internal power supply Overvoltage threshold VBAT Delay time overvoltage Overvoltage threshold hysteresis VBAT Undervoltage threshold VBAT Delay time undervoltage Undervoltage threshold hysteresis VBAT ON resistance of VBAT switch Resistor defining internal bias currents used for internal timings, regardless of watchdog timing Measured during qualification only VVBAT = 13.5V Measured during qualification only VVBAT = 13.5V(1) IVBAT1 IVCC IVBAT2 VINT VBG VTHOV tOV VTOVhys VTHUV tUV VTUVhys RON_VBATSW 6 16 0.4 1 4.75 1.21 25 16 0.7 6.5 7 35 35 5 1.26 7 3 70 5.25 1.33 29 35 mA mA A V V V s V V s V k
Current consumption VCC VVCC = 5V(1) VVBAT = 13.5V(3) VVBAT 5.2V
Buffered band-gap voltage VVBAT 5V(2)
1.13
Tolerance: 1%
RVREF
20
k
* Type: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Notes: 1. EN, DIR, PWM = HIGH 2. Internal band-gap voltage is valid for VBAT > 3V (not testable) 3. Valid for -40C to +90C 4. RSHUNT = 1 5. Tested during qualification only 6. For timing, see the formula in "Reset and Watchdog Management" on page 8. All times depend on external elements CCWD and RCWD, tolerances of these elements have to be added to the given tolerances in the above table 7. External parasitic capacitive load together with pull-up resistor at RX defines the time tRxH 8. If single-ended mode is used (SEM = HIGH): DATA is not used and VBAT / 2 instead of DATA is the internal reference for parameters 4.10 and 4.11 9. Maximum voltage difference arises during slope, see Figure 7-1 on page 30 10. Parameters 4.16 to 4.19 are based on transmit voltage slopes at DATA and /DATA of 4V/s 50%
20
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4865C-AUTO-01/06
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7. Electrical Characteristics (Continued)
All parameters given are valid for 7V VBAT 40V and for -40C ambient 125C unless stated otherwise. Conditions: SEM = HIGH (single-ended mode of SCI). No. 2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 3 3.1 3.2 3.3 Parameters 2.2V-5V Regulator Regulated output voltage Regulated output voltage Line regulation Load regulation VVBAT > 9V Iload = 0 mA to 100 mA 6V < VVBAT 9V Iload = 0 mA to 50 mA Iload = 0 mA to 100 mA VVBAT > 9V Iload = 0 mA to 100 mA
(4)
Test Conditions
Pin
Symbol
Min
Typ
Max
Unit
Type*
VCC1 VCC2 linereg loadreg IOS1 IOS2 IVREG RESR
4.85 4.5
5.15 5.5 100 100
V V mV mV mA mA mA F
Output current limitation(4) VVBAT > 9V Output current limitation Output current VREG ESR value of used blocking capacitor Blocking capacitor at VCC Current gain of external NPN Reset and Watchdog VCC threshold voltage level for /RESET VCC threshold voltage level for /RESET Hysteresis of /RESET level Length of pulse at /RESET pin /RESET pulse triggered by watchdog, CCWD = 1 nF RCWD = 56 k Combination with HF capacitor of 100 nF 6V < VVBAT 9V VVREG = 5V, VVCC = 0V, VVBAT = 9V
100 50 3 0.3 40 25
400 400 20 3
CVCC BN
VtHRESH VtHRESL HYSRESth
4.2 3.8 0.4(5)
4.6 4.15
V V V
3.4
tRES
2.58
2.96
ms
* Type: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Notes: 1. EN, DIR, PWM = HIGH 2. Internal band-gap voltage is valid for VBAT > 3V (not testable) 3. Valid for -40C to +90C 4. RSHUNT = 1 5. Tested during qualification only 6. For timing, see the formula in "Reset and Watchdog Management" on page 8. All times depend on external elements CCWD and RCWD, tolerances of these elements have to be added to the given tolerances in the above table 7. External parasitic capacitive load together with pull-up resistor at RX defines the time tRxH 8. If single-ended mode is used (SEM = HIGH): DATA is not used and VBAT / 2 instead of DATA is the internal reference for parameters 4.10 and 4.11 9. Maximum voltage difference arises during slope, see Figure 7-1 on page 30 10. Parameters 4.16 to 4.19 are based on transmit voltage slopes at DATA and /DATA of 4V/s 50%
21
4865C-AUTO-01/06
7. Electrical Characteristics (Continued)
All parameters given are valid for 7V VBAT 40V and for -40C ambient 125C unless stated otherwise. Conditions: SEM = HIGH (single-ended mode of SCI). No. 3.5 Parameters Delay time of release /RESET after VCC exceeding VtHRESH Test Conditions CCWD = 1 nF RCWD = 56 k(6) Pin Symbol tdelayRESH tdelayRESL t tdelayRESH tow1 tow tCW RCWD CCWD VILWD VIHWD VhysWD tWpL / tWpH tWDr tWDf 1000 100 100 0.7 x VVCC 1 Min 2.58 Typ Max 2.96 Unit ms Type*
3.6 3.7 3.8
Time for VCC < VtHRESL Independent of CCWD before activating /RESET and RCWD Watchdog oscillator period CCWD = 1 nF RCWD = 56 k(6)
0.5 60.4 2.6
2 68.8 3.0
s s ms
CCWD = 1 nF Time for VCC > VtHRESH before release of /RESET RCWD = 56 k(6) First open watchdog = 1 nF C window width after power- CWD RCWD = 56 k(6) on Open watchdog window width CCWD = 1 nF RCWD = 56 k(6)
3.9
50.2
57.2
ms
3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19
11.2 11.2 10 470
12.7 12.7 100 3300 0.3 x VVCC
ms ms k pF V V V ns ns ns
Closed watchdog window CCWD = 1 nF width RCWD = 56 k(6) External watchdog resistor External watchdog capacitor Watchdog input low voltage threshold Watchdog input high voltage threshold Hysteresis of watchdog input voltage threshold Pulse length of watchdog Measured between pulse for proper triggering 50% levels Rise time of watchdog trigger pulse Fall time of watchdog trigger pulse
* Type: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Notes: 1. EN, DIR, PWM = HIGH 2. Internal band-gap voltage is valid for VBAT > 3V (not testable) 3. Valid for -40C to +90C 4. RSHUNT = 1 5. Tested during qualification only 6. For timing, see the formula in "Reset and Watchdog Management" on page 8. All times depend on external elements CCWD and RCWD, tolerances of these elements have to be added to the given tolerances in the above table 7. External parasitic capacitive load together with pull-up resistor at RX defines the time tRxH 8. If single-ended mode is used (SEM = HIGH): DATA is not used and VBAT / 2 instead of DATA is the internal reference for parameters 4.10 and 4.11 9. Maximum voltage difference arises during slope, see Figure 7-1 on page 30 10. Parameters 4.16 to 4.19 are based on transmit voltage slopes at DATA and /DATA of 4V/s 50%
22
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7. Electrical Characteristics (Continued)
All parameters given are valid for 7V VBAT 40V and for -40C ambient 125C unless stated otherwise. Conditions: SEM = HIGH (single-ended mode of SCI). No. 3.20 3.21 3.22 4 4.1 4.2 4.3 Parameters Output low voltage of /RESET Internal pull-up resistor at pin /RESET Leakage current WD pin SCI Transceiver Rx output voltage HIGH IRx = 0 VRxH RRXH RRXL tRxH tRxL VTxL VTxH
(5)
Test Conditions At IOLRES = 1 mA
Pin
Symbol VOLRES RPURES
Min
Typ
Max 0.4
Unit V k A V k s
Type*
5 -10 4.5 5
10
15 +10 5.5
VWD = 0V to VCC
IleakWD
Internal pull-up resistance VRx = 0, driver set to to VCC HIGH RDS_ON of low-side driver transistor of RX output Output HIGH delay time Driver set to LOW See Figure 3-7 and Figure 3-8 on page 12(7) See Figure 3-7 and Figure 3-8 on page 12
10 40
20 90
4.4
0.5
4.5 4.6 4.7 4.8 4.9
Output LOW delay time Tx input LOW level Tx input HIGH level Input hysteresis Tx Internal pull-up resistance to VCC Input high voltage difference between DATA and /DATA Input low voltage difference between DATA and /DATA Hysteresis between VDATH and VDATL
0.5 0.3 x VVCC 0.7 x VVCC 1 10 20 40 5% of VVBAT -5% of VVBAT 5% of VVBAT
s V V V k
VhysTx RTXH
4.10
(8)
VRDATH
V
4.11
(8)
VRDATL VDAThys
V
4.12
(5)
V
* Type: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Notes: 1. EN, DIR, PWM = HIGH 2. Internal band-gap voltage is valid for VBAT > 3V (not testable) 3. Valid for -40C to +90C 4. RSHUNT = 1 5. Tested during qualification only 6. For timing, see the formula in "Reset and Watchdog Management" on page 8. All times depend on external elements CCWD and RCWD, tolerances of these elements have to be added to the given tolerances in the above table 7. External parasitic capacitive load together with pull-up resistor at RX defines the time tRxH 8. If single-ended mode is used (SEM = HIGH): DATA is not used and VBAT / 2 instead of DATA is the internal reference for parameters 4.10 and 4.11 9. Maximum voltage difference arises during slope, see Figure 7-1 on page 30 10. Parameters 4.16 to 4.19 are based on transmit voltage slopes at DATA and /DATA of 4V/s 50%
23
4865C-AUTO-01/06
7. Electrical Characteristics (Continued)
All parameters given are valid for 7V VBAT 40V and for -40C ambient 125C unless stated otherwise. Conditions: SEM = HIGH (single-ended mode of SCI). No. 4.13 4.14 4.15 4.16 4.17 4.18 4.19 4.20 4.21 4.22 4.23 4.24 4.25 4.26 4.27 4.28 4.29 4.30 Parameters Output HIGH voltage pin DATA Output HIGH voltage pin DATA Output LOW voltage pin /DATA Output LOW voltage pin /DATA Short-circuit current /DATA Short-circuit current DATA SEM input LOW level SEM input HIGH level Input hysteresis SEM Internal pull-up resistance to VCC Transmit delay HIGH to LOW(10) Transmit fall time(10) Transmit delay LOW to HIGH(10) Transmit rise time(10) Activation voltage on /DATA of SCI receive part Input current pin DATA for -2V < VDATA < passive transmit VVBAT - 2V Filter time for wake-up via SCI Input current pin DATA for VDATA VVBAT - 0.5 passive transmit VVBAT = 13.5V VVBAT = 13.5V VVBAT = 13.5V VVBAT = 13.5V
(5)
Test Conditions TX = LOW, IDATA = -20 mA TX = LOW, IDATA = -40 mA TX = LOW, I/DATA = 20 mA TX = LOW, I/DATA = 40 mA
Pin
Symbol VTDATAH1 VTDATAH2 VT/DATAL1 VT/DATAL2 I/DATASC IDATASC VSEML VSEMH VhysSEM RSEM tSCL tSCf tSCH tSCr V/DATwake IDATA1 twakeSCI IDATA2
Min VVBAT - 1.2 VVBAT - 1.5
Typ
Max
Unit V V
Type*
1.2 1.5 40 -40 75 -75 150 -150 0.3 x VVCC 0.7 x VVCC 1 10 0 1.5 0 1.5 1 20 1 40 1.5 4.1 1.5 4.1 VVBAT - 2 -20 30 +20 80 500
V V mA mA V V V k s s s s V A s A
* Type: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Notes: 1. EN, DIR, PWM = HIGH 2. Internal band-gap voltage is valid for VBAT > 3V (not testable) 3. Valid for -40C to +90C 4. RSHUNT = 1 5. Tested during qualification only 6. For timing, see the formula in "Reset and Watchdog Management" on page 8. All times depend on external elements CCWD and RCWD, tolerances of these elements have to be added to the given tolerances in the above table 7. External parasitic capacitive load together with pull-up resistor at RX defines the time tRxH 8. If single-ended mode is used (SEM = HIGH): DATA is not used and VBAT / 2 instead of DATA is the internal reference for parameters 4.10 and 4.11 9. Maximum voltage difference arises during slope, see Figure 7-1 on page 30 10. Parameters 4.16 to 4.19 are based on transmit voltage slopes at DATA and /DATA of 4V/s 50%
24
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ATA6026
7. Electrical Characteristics (Continued)
All parameters given are valid for 7V VBAT 40V and for -40C ambient 125C unless stated otherwise. Conditions: SEM = HIGH (single-ended mode of SCI). No. 4.31 4.32 5 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 5.10 5.11 5.12 5.13 5.14 Parameters Test Conditions Pin Symbol I/DATA VSYM Min -20 2.5 Typ Max +20 Unit A V Type* Input current pin /DATA for -2V < V/DATA < VVBAT + 2V passive transmit Symmetry of DATA and /DATA during transmit Enable input low-voltage threshold Enable input high-voltage threshold Hysteresis of EN switching level Pull-down resisistor at Enable pin DIR input low-voltage threshold DIR input high-voltage threshold Hysteresis of DIR switching level Pull-down resisistor at DIR pin PWM input low-voltage threshold PWM input high-voltage threshold Hysteresis of PWM switching level Pull-down resisistor at PWM pin Rise/fall time, pin EN Rise/fall time, pin PWM Tested during characterization only Tested during characterization only Tested during characterization only VVBAT = 13.5V(9)
Control Inputs EN, DIR, PWM VILEN VIHEN HYSENth RPDEN VILDIR VIHDIR HYSDIRth RPDDIR VILPWM VIHPWM HYSPWMth RPDPWM trf_EN trf_PWM 30 0.7 x VVCC 1 100 100 100 30 0.7 x VVCC 1 100 0.3 x VVCC 30 3.5 0.7 100 0.3 x VVCC 2 V V V k V V V k V V V k ns ns
* Type: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Notes: 1. EN, DIR, PWM = HIGH 2. Internal band-gap voltage is valid for VBAT > 3V (not testable) 3. Valid for -40C to +90C 4. RSHUNT = 1 5. Tested during qualification only 6. For timing, see the formula in "Reset and Watchdog Management" on page 8. All times depend on external elements CCWD and RCWD, tolerances of these elements have to be added to the given tolerances in the above table 7. External parasitic capacitive load together with pull-up resistor at RX defines the time tRxH 8. If single-ended mode is used (SEM = HIGH): DATA is not used and VBAT / 2 instead of DATA is the internal reference for parameters 4.10 and 4.11 9. Maximum voltage difference arises during slope, see Figure 7-1 on page 30 10. Parameters 4.16 to 4.19 are based on transmit voltage slopes at DATA and /DATA of 4V/s 50%
25
4865C-AUTO-01/06
7. Electrical Characteristics (Continued)
All parameters given are valid for 7V VBAT 40V and for -40C ambient 125C unless stated otherwise. Conditions: SEM = HIGH (single-ended mode of SCI). No. 5.15 5.16 5.17 6 6.1 6.2 Parameters Rise/fall time, pin DIR Delay time for "Go to Active" by Enable Delay time for "Go to Sleep" by Enable Charge Pump Charge pump voltage Charge pump voltage Charge pump current driving capability under valid parameters 6.1/6.2 Charge pump oscillator frequency Serial resistance between charge pump and gate of external reverse battery protection NMOS Charge pump voltage in case of EN = 0 H-bridge Driver Low-side driver HIGH output voltage Low-side driver HIGH output voltage ON resistance of sink stage of pins L1, L2 ON resistance of source stage of pins L1, L2 Related to pin CBx 6V< VVBAT 9V VVBAT > 9V (with VVBAT > 25V drivers may be switched off) VLxH1 VLxH2 RDSON_LxL, x = 1,2 RDSON_LxH, x = 1,2 VVBAT - 1 8 16 V EN = "0" (Sleep mode) 7V VVBAT 9V VVBAT > 9V VCP VCP VVBAT + 7 VVBAT + 8 50 VVBAT + 14 VVBAT + 14 V V Test Conditions Pin Symbol trf_DIR tdelON_EN tgotosleep 30 30 Min Typ Max 100 80 80 Unit ns s s Type*
6.3
ICP fcposc
A
6.4
2.2
MHz
6.5
RCP
10
k
6.6 7 7.1
VCPsleep
VVBAT - 0.7V
7.2
16
V
7.3 7.4
20 30
* Type: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Notes: 1. EN, DIR, PWM = HIGH 2. Internal band-gap voltage is valid for VBAT > 3V (not testable) 3. Valid for -40C to +90C 4. RSHUNT = 1 5. Tested during qualification only 6. For timing, see the formula in "Reset and Watchdog Management" on page 8. All times depend on external elements CCWD and RCWD, tolerances of these elements have to be added to the given tolerances in the above table 7. External parasitic capacitive load together with pull-up resistor at RX defines the time tRxH 8. If single-ended mode is used (SEM = HIGH): DATA is not used and VBAT / 2 instead of DATA is the internal reference for parameters 4.10 and 4.11 9. Maximum voltage difference arises during slope, see Figure 7-1 on page 30 10. Parameters 4.16 to 4.19 are based on transmit voltage slopes at DATA and /DATA of 4V/s 50%
26
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7. Electrical Characteristics (Continued)
All parameters given are valid for 7V VBAT 40V and for -40C ambient 125C unless stated otherwise. Conditions: SEM = HIGH (single-ended mode of SCI). No. 7.5 Parameters Output peak current at pins L1, L2 switched to LOW Output peak current at pins L1, L2 switched to HIGH Pull-down resistance at pins L1, L2 ON resistance of sink stage of pins H1, H2 ON resistance of source stage of pins H1, H2 VSx = 0 Related to pin CBx, VSx = VVBAT Test Conditions VLx = 3V Pin Symbol ILxL, x = 1,2 ILxH, x = 1,2 RPDLx, x = 1,2 RDSON_HxL, x = 1,2 RDSON_HxH, x = 1,2 IHxL, x = 1,2 30 Min 100 Typ Max Unit mA Type*
7.6
VLx = 3V
-100
mA
7.7 7.8 7.9
100 20 30
k
7.10
VVBAT = 13.5V Output peak current at VSx = VVBAT pins Hx, switched to LOW VCBx = VVBAT + 7V VHx = VVBAT + 3V VVBAT = 13.5V Output peak current at VSx = VVBAT pins Hx, switched to HIGH VCBx = VVBAT + 7V VHx = VVBAT + 3V Static high-side switch VSx = 0V output low-voltage pins Hx IHx = 1 mA Static high-side switch output high-voltage pins H1, H2 Static high-side switch output high-voltage pins H1, H2 Sink resistance between Hx and Ground in Sleep mode ILx = -10 A (PWM = static) 7V VVBAT 9V ILx = -10 A (PWM = static) VVBAT > 9V (with VVBAT > 25V, drivers may be switched off)
100
mA
7.11
IHxH, x = 1,2 VHxL, x = 1,2 VHxHstat1 (supplied by VVBAT + 7 charge pump) VHxHstat1 (supplied by VVBAT + 8 charge pump)
-100
mA
7.12
0.3 VVBAT + 14
V
7.13
V
7.14
VVBAT + 14
V
7.15
RHxsleep
3
10
k
* Type: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Notes: 1. EN, DIR, PWM = HIGH 2. Internal band-gap voltage is valid for VBAT > 3V (not testable) 3. Valid for -40C to +90C 4. RSHUNT = 1 5. Tested during qualification only 6. For timing, see the formula in "Reset and Watchdog Management" on page 8. All times depend on external elements CCWD and RCWD, tolerances of these elements have to be added to the given tolerances in the above table 7. External parasitic capacitive load together with pull-up resistor at RX defines the time tRxH 8. If single-ended mode is used (SEM = HIGH): DATA is not used and VBAT / 2 instead of DATA is the internal reference for parameters 4.10 and 4.11 9. Maximum voltage difference arises during slope, see Figure 7-1 on page 30 10. Parameters 4.16 to 4.19 are based on transmit voltage slopes at DATA and /DATA of 4V/s 50%
27
4865C-AUTO-01/06
7. Electrical Characteristics (Continued)
All parameters given are valid for 7V VBAT 40V and for -40C ambient 125C unless stated otherwise. Conditions: SEM = HIGH (single-ended mode of SCI). No. 7.16 7.17 7.18 7.19 7.20 7.21 7.22 7.23 7.24 Parameters Test Conditions Pin Symbol VSxOFF VCB1 VCB1 VCB1 VCB1 VCB2 VCB2 VCB2 VCB2 5 7 9 9 5 7 9 9 Min Typ Max 2 14 14 14 14 14 14 14 14 Unit V V V V V V V V V Type* Voltage at pin Sx for open pin if Hx and Lx are both Isx = 0 switched off CB1 voltage for H1 = OFF VVBAT = 6V CB1 voltage for H1 = OFF VVBAT = 8V CB1 voltage for H1 = OFF VVBAT = 10V CB1 voltage for H1 = OFF VVBAT = 25V CB2 voltage for H2 = OFF VVBAT = 6V CB2 voltage for H2 = OFF VVBAT = 8V CB2 voltage for H2 = OFF VVBAT = 10V CB2 voltage for H2 = OFF VVBAT = 25V Dynamic Parameters Dynamic high-side switch output for high-voltage pins H1, H2 (bootstrap voltage) Dynamic high-side switch output for high-voltage pins H1, H2 (bootstrap voltage) Dynamic high-side switch output for high-voltage pins H1, H2 (bootstrap voltage) CHx = 5 nF CCBx = 100 nF fPWM = 20 kHz VVBAT = 6V CHx = 5 nF CCBx = 100 nF fPWM = 20 kHz VVBAT = 8V CHx = 5nF CCBx = 100 nF fPWM = 20 kHz VVBAT 10V VVBAT + 4.5 VVBAT + 14
7.14
VHxHdyn1
V
7.15
VHxHdyn2
VVBAT + 6
VVBAT + 14
V
7.16
VHxHdyn3
VVBAT + 8
VVBAT + 14
V
7.17
Propagation delay time for VVBAT = 13.5V low-side driver from HIGH CCBx = 100 nF Figure 3-9 on page 17 to LOW Propagation delay time for low-side driver from LOW to HIGH Fall time for low-side driver VVBAT = 13.5V CGx = 5 nF
tLxHL
0.5
s
7.18
tLxLH tLxf
0.5 + tCC 0.5
s
7.19
s
* Type: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Notes: 1. EN, DIR, PWM = HIGH 2. Internal band-gap voltage is valid for VBAT > 3V (not testable) 3. Valid for -40C to +90C 4. RSHUNT = 1 5. Tested during qualification only 6. For timing, see the formula in "Reset and Watchdog Management" on page 8. All times depend on external elements CCWD and RCWD, tolerances of these elements have to be added to the given tolerances in the above table 7. External parasitic capacitive load together with pull-up resistor at RX defines the time tRxH 8. If single-ended mode is used (SEM = HIGH): DATA is not used and VBAT / 2 instead of DATA is the internal reference for parameters 4.10 and 4.11 9. Maximum voltage difference arises during slope, see Figure 7-1 on page 30 10. Parameters 4.16 to 4.19 are based on transmit voltage slopes at DATA and /DATA of 4V/s 50%
28
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7. Electrical Characteristics (Continued)
All parameters given are valid for 7V VBAT 40V and for -40C ambient 125C unless stated otherwise. Conditions: SEM = HIGH (single-ended mode of SCI). No. 7.20 Parameters Rise time for low-side driver Propagation delay time for VVBAT = 13.5V high-side driver from CCBx = 100 nF HIGH to LOW Figure 3-9 on page 17 Propagation delay time for high-side driver from LOW to HIGH Fall time for high-side driver Rise time for high-side driver Cross conduction time External resistor External capacitor RON of tCC switching transistor Switching level of tCC comparator Short circuit detection voltage Voltage between source-drain of external switching transistor in active case See "Cross Conduction Time" on page 16 VVBAT = 13.5V CGx = 5 nF Test Conditions Pin Symbol tLxr tHxHL Min Typ Max 0.5 Unit s Type*
7.21
0.5
s
7.22
tHxLH tHxf tHxr tCC RCC CCC RONCC Vswtcc 3.2 x VVCC 3.5 3.4 x VVCC 4 5
0.5 + tCC 0.5 0.5 10
s
7.23 7.24 7.25 7.26 7.27 7.28 7.29
s s s k
5 100 3.6 x VVCC 4.5
nF V
7.30
VSC
V
* Type: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Notes: 1. EN, DIR, PWM = HIGH 2. Internal band-gap voltage is valid for VBAT > 3V (not testable) 3. Valid for -40C to +90C 4. RSHUNT = 1 5. Tested during qualification only 6. For timing, see the formula in "Reset and Watchdog Management" on page 8. All times depend on external elements CCWD and RCWD, tolerances of these elements have to be added to the given tolerances in the above table 7. External parasitic capacitive load together with pull-up resistor at RX defines the time tRxH 8. If single-ended mode is used (SEM = HIGH): DATA is not used and VBAT / 2 instead of DATA is the internal reference for parameters 4.10 and 4.11 9. Maximum voltage difference arises during slope, see Figure 7-1 on page 30 10. Parameters 4.16 to 4.19 are based on transmit voltage slopes at DATA and /DATA of 4V/s 50%
29
4865C-AUTO-01/06
7. Electrical Characteristics (Continued)
All parameters given are valid for 7V VBAT 40V and for -40C ambient 125C unless stated otherwise. Conditions: SEM = HIGH (single-ended mode of SCI). No. Parameters Short circuit detection time Test Conditions For switch-on time < tsc, the short circuit message will never be generated Time for Lx = ON (plus cross conduction time if inductive load is applied), this time limits the PWM ratio to values of about 95% if 20 kHz is used Pin Symbol Min Typ Max Unit Type*
7.31
tSC
5
10
15
s
7.32
Charging time for bootstrap capacitors
tCHBOOT
1.3
s
7.33
Maximum PWM frequency
fPWMmax
30
kHz
* Type: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Notes: 1. EN, DIR, PWM = HIGH 2. Internal band-gap voltage is valid for VBAT > 3V (not testable) 3. Valid for -40C to +90C 4. RSHUNT = 1 5. Tested during qualification only 6. For timing, see the formula in "Reset and Watchdog Management" on page 8. All times depend on external elements CCWD and RCWD, tolerances of these elements have to be added to the given tolerances in the above table 7. External parasitic capacitive load together with pull-up resistor at RX defines the time tRxH 8. If single-ended mode is used (SEM = HIGH): DATA is not used and VBAT / 2 instead of DATA is the internal reference for parameters 4.10 and 4.11 9. Maximum voltage difference arises during slope, see Figure 7-1 on page 30 10. Parameters 4.16 to 4.19 are based on transmit voltage slopes at DATA and /DATA of 4V/s 50%
Figure 7-1.
Principal Dynamic Behavior of SCI, VSYM is the Symmetry of DATA and /DATA to VBAT / 2
VBAT DATA
VBAT/2
/DATA GND
VSYM = (VBAT - /DATA) - DATA, ideally it should always be 0
30
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ATA6026
8. ESD and Latch-up Requirements
The device withstands pulses when tested according to ESD STM 5.1-1998: * Constant voltage 2 kV * R = 1.5 k * C = 100 pF * 1 pulse per polarity and per pin * 3 samples, 0 failures * Electrical post-stress testing at room temperature Static latch-up tested according to AEC-Q100-004 and JESD78. * 3-6 samples, 0 failures * Electrical post-stress testing at room temperature In test, the voltage at the pins VBAT, DATA, /DATA, CP, VBAT_SWITCH, Hx, Sx, CBx must not exceed 45V in case of not being able to drive the specified current; for the pins Lx the voltage must not exceed 25V.
31
4865C-AUTO-01/06
9. Ordering Information
Extended Type Number ATA6026-PHQW Package QFN32, 7 mm x 7 mm Remarks Pb-free
10. Package Information
Thermal resistance junction ambient: 29 K/W (at airflow of 0 LFPM), valid for JEDEC Standard Four-layer Thermal Test Board with 5 x 5 Thermal Via Matrix (100 m Drill Hole, Filled Vias).
32
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11. Table of Contents
Features ..................................................................................................... 1 1 2 3 Description ............................................................................................... 1 Pin Configuration ..................................................................................... 3 Functional Description ............................................................................ 5
3.1 Power Supply Unit ....................................................................................................5 3.2 Sleep Mode ..............................................................................................................5 3.3 Wake-up and Sleep Mode Strategy .........................................................................6 3.4 5V Regulator ............................................................................................................7 3.5 Reset and Watchdog Management ..........................................................................8 3.6 SCI Transceiver ......................................................................................................11 3.7 Control Inputs EN, DIR, PWM ................................................................................13 3.8 Diagnosis ................................................................................................................14 3.9 Behavior of the Bridge Drivers in Case of RESET .................................................15 3.10 Charge Pump .......................................................................................................16 3.11 H-bridge Driver .....................................................................................................16
4 5 6 7 8 9
Absolute Maximum Ratings .................................................................. 18 Operating Range .................................................................................... 19 Temperature Conditions ....................................................................... 19 Electrical Characteristics ...................................................................... 20 ESD and Latch-up Requirements ......................................................... 31 Ordering Information ............................................................................. 32
10 Package Information ............................................................................. 32
33
4865C-AUTO-01/06
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